The present invention relates to a microcomputer and, more particularly, to a microcomputer having an electrically erasable and programmable nonvolatile memory (called hereinafter "E.sup.2 PROM") as a data memory.
A random access memory (RAM) is generally employed as a data memory of a microcomputer, which stores data to be processed and processed resultant data. However, a RAM has an unavoidable problem that data stored therein are destroyed when a power voltage supplied thereto is cut off. Therefore, an E.sup.2 PROM is typically employed as a part of the data memory to store and hold data which are required to be kept stored even after a power voltage is cut off.
A data write process to an E.sup.2 PROM consists of an erasing operation, which is first performed to initialize the memory cell at an address to be written with new data by erasing the data formerly stored at that address, and a writing operation, which is subsequently performed to write the new data into that address. As is well known in the art, the erasing and writing operations require a relatively long time duration, about 10 msec, respectively. This time duration is extremely long in comparison with an instruction execution time or a machine cycle time of a CPU (Central Processing Unit). If a CPU is programmed to perform the data write process to E.sup.2 PROM, the execution efficiency of the program is deteriorated substantially.
In order to solve this problem, an erasing and writing automation circuit is provided to control the data write process to an E.sup.2 PROM in place of a CPU. When the CPU receives a data write instruction to the E.sup.2 PROM, it issues the automation circuit with a data write request including a write address, data to be written (i.e., write data) and a write command signal. The CPU is thereafter shifted to a subsequent operation to execute other instructions.
On the other hand, the erasing and writing automation circuit is initiated by the data write request to first perform the erasing operation in which a so-called V.sub.pp voltage higher than a power voltage applied to the CPU is applied to memory cells of the selected address of the E.sup.2 PROM for the above-mentioned relatively long period. The data, which have been stored in those memory cells, are thereby erased. When the erasing operation is completed, the writing operation is performed to apply the Vpp voltage or ground voltage to the selected memory cells in accordance with data to be written for the relatively long period. The new data is thereby stored in the selected memory cells. In order to detect each of the erasing and writing operation time durations, the automation circuit includes a timer for counting a reference clock signal and generating an operation end signal when a predetermined time has elapsed. In response to this operation end signal, the application of the Vpp voltage to the selected memory cells is terminated to thereby complete the erasing and writing operations.
Since the CPU executes subsequent instructions in parallel to the data write process, by the automation circuit, a situation will occur in which the CPU encounters a data read instruction for reading data from the E.sup.2 PROM. Since the data read operation for reading data from the E.sup.2 PROM can be performed at a high speed, similarly to the data read operation from RAM, the data read instruction for reading data from E.sup.2 PROM is executed immediately without waiting until the current data write process to E.sup.2 PROM is completed. When the CPU executes the data read instruction for reading out from the E.sup.2 PROM, it issues the automation circuit with a data read request including read address information and a read command; signal. In response to this request, the automation circuit suspends the data write process and then brings the E.sup.2 PROM into a data read operation mode. An address of the E.sup.2 PROM selected by the read address information is accessed and data stored therein is then transferred to the CPU. The suspended data write process is thereafter resumed.
Thus, the data write process may be temporarily suspended by the data read request issued from the CPU. However, the automation circuit automatically completes the erasing and writing operations in response to the operation end signal generated by the timer. For this reason, the application time of the Vpp voltage to the selected memory cells is shortened by the suspended time of the data write process. The data is thereby not fully written into the E.sup.2 PROM. This drawback can be solved by initializing or resetting the timer in response to the data read request. However, in that case, the data write process is again performed from the beginning, so that a time for preforming the data write process is prolonged undesirably.